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1 fn3096.6 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2001, 2008, 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. hi-574a, hi-674a complete, 12-bit a/d converters with microprocessor interface the hi-x74(a) is a complete 12-bit, analog-to-digital converter, including a +10v reference clock, three-state outputs and a digital interface for microprocessor control. successive approximation conversion is performed by two monolithic dice housed in a 28 lead package. the bipolar analog die features the intersil dielectric isolation process, which provides enhanced ac performance and freedom from latch-up. custom design of each ic (bipolar analog and cmos digital) has yielded improved performance over existing versions of this converter. the voltage comparator features high psrr plus a high speed current-mode latch, and provides precise decisions down to 0.1 lsb of in put overdrive. more than 2x reduction in noise has been achieved by using current instead of voltage for transmission of all signals between the analog and digital ics. also, the clock oscillator is current controlled for excellent stability over temperature. the hi-x74(a) offers standard unipolar and bipolar input ranges, laser trimmed for specified linearity, gain and offset accuracy. the low noise buried zener reference circuit is trimmed for minimum temperature coefficient. power requirements are +5v and 12v to 15v, with typical dissipation of 385mw (hi-574a, hi-674a) at 12v. features ? complete 12-bit a/d converter with reference and clock ? full 8-bit, 12-bit or 16-bit microprocessor bus interface ? bus access time . . . . . . . . . . . . . . . . . . . . . . . . . . . 150ns ? no missing codes over temperature ? minimal setup time for control signals ? fast conversion times - hi-574a (max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25s - hi-674a (max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15s ? low noise, via current-mode signal transmission between chips ? byte enable/short cycle (a o input) - guaranteed break-before-make action, eliminating bus contention during read operation. latched by start convert input (to set the conversion length) ? supply voltage . . . . . . . . . . . . . . . . . . . . . . 12v to 15v ? pb-free available (rohs compliant) applications ? military and industrial data acquisition systems ? electronic test and scientific instrumentation ? process control systems pinout hi-574a, hi-674a (28 ld pdip, sbdip) top view status, sts db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 dig common, digital data outputs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 chip enable, ce +10v ref, ref out reference input 20v input analog common, ac +12v/+15v supply, v cc byte addr/short cycle, a o 10v input +5v supply, v logic chip sel, cs data mode sel, 12/8 read/convert, r/c bipolar offset bip off -12v/-15v supply, v ee msb lsb dc data sheet august 7, 2008 n o t r e c o m m e n d e d f o r n e w d e s i g n s p o s s i b l e s u b s t i t u t e p r o d u c t i s l 2 6 3 x x a n d i s l 2 6 7 x x f a m i l i e s w w w . i n t e r s i l . c o m / c o n v e r t e r s / # p r o d u c t s
2 fn3096.6 august 7, 2008 ordering information part number part marking inl temperature range (c) package pkg. dwg. # hi3-574ajn-5 hi3-574ajn-5 1.0 lsb 0 to +75 28 ld pdip e28.6 hi3-574ajn-5z (notes 1, 3) hi3-574ajn-5z 1.0 lsb 0 to +75 28 ld pdip (pb-free) e28.6 hi3-574akn-5 hi3-574akn-5 0.5 lsb 0 to +75 28 ld pdip e28.6 hi3-574akn-5z (notes 1, 3) hi3-574akn-5z 0.5 lsb 0 to +75 28 ld pdip (pb-free) e28.6 hi1-574ajd-5 (note 2) hi1-574ajd -5 1.0 lsb 0 to +75 28 ld sbdip (pb-free) d28.6 hi1-574akd-5 (note 2) hi1-574akd -5 0.5 lsb 0 to +75 28 ld sbdip (pb-free) d28.6 hi1-574asd-2 (note 2) hi1-574asd -2 1.0 lsb -55 to +125 28 ld sbdip (pb-free) d28.6 hi1-574atd-2 (note 2) hi1- 574atd-2 0.5 lsb -55 to +125 28 ld sbdip (pb-free) d28.6 hi3-674ajn-5 hi3-674ajn-5 1.0 lsb 0 to +75 28 ld pdip e28.6 hi3-674ajn-5z (notes 1, 3) hi3-674ajn-5z 1.0 lsb 0 to +75 28 ld pdip (pb-free) e28.6 hi3-674akn-5 hi3-674akn-5 0.5 lsb 0 to +75 28 ld pdip e28.6 hi3-674akn-5z (notes 1, 3) hi3-674akn-5z 0.5 lsb 0 to +75 28 ld pdip (pb-free) e28.6 hi1-674akd-5 (note 2) hi1-674akd -5 0.5 lsb 0 to +75 28 ld sbdip (pb-free) d28.6 HI1-674ATD/883 (note 2) HI1-674ATD /883 0.5 lsb -55 to +125 28 ld sbdip (pb-free) d28.6 notes: 1. pb-free pdips can be used for through hole wave solder processi ng only. they are not intended for use in reflow solder proces sing applications. 2. these intersil pb-free hermetic packaged pr oducts employ 100% au plate - e4 termi nation finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. 3. these intersil pb-free plastic packaged produc ts employ special pb-free material sets , molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible with both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std- 020. hi-574a, hi-674a
3 fn3096.6 august 7, 2008 functional block diagram bit outputs msb lsb nibble b (note) nibble c (note) nibble a (note) power-up reset three-state buffers and control 12 bits sar strobe digital chip control clk oscillator logic analog chip dac 10k +10v ref - + 5k 5k 5k 2.5k 10v input 20v input bip off analog common comp - + 12/ 8 cs a o r/ c ce v ref in v ref out v logic digital common sts v cc v ee 10k note: ?nibble? is a 4-bit digital word. 12 bits hi-574a, hi-674a
4 fn3096.6 august 7, 2008 absolute maximum rati ngs thermal information supply voltage v cc to digital common . . . . . . . . . . . . . . . . . . . . . . 0v to +16.5v v ee to digital common . . . . . . . . . . . . . . . . . . . . . . . 0v to -16.5v v logic to digital common . . . . . . . . . . . . . . . . . . . . . . 0v to +7v analog common to digital common . . . . . . . . . . . . . . . . . . . .1v control inputs (ce, cs , a o , 12/8 , r/c ) to digital common . . -0.5v to v logic +0.5v analog inputs (refin, bipoff, 10vin) to analog common . . . . . . . . . . 16.5v 20vin to analog common . . . . . . . . . . . . . . . . . . . . . . . . . . 24v refout . . . . . indefinite short to common, momentary short to v cc operating conditions temperature range hi3-574axx-5, hi1-674axx-5 . . . . . . . . . . . . . . . . . . 0c to +75c hi1-574axd-2, hi1-674axd-2 . . . . . . . . . . . . . . .-55c to +125c thermal resistance (typical, note 4) ja (c/w) jc (c/w) sbdip package . . . . . . . . . . . . . . . . . . 55 18 pdip package* . . . . . . . . . . . . . . . . . . . 60 n/a maximum junction temperature pdip package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150c sbdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175c maximum storage temperature range pdip package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c sbdip package . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp *pb-free pdips can be used for through hole wave solder processing only. they are not intended for use in reflow solder processing applications. die characteristics transistor count hi-574a, hi-674a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117 caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 4. ja is measured with the component mounted on a low effective therma l conductivity test board in free air. see tech brief tb379 fo r details. dc and transfer accuracy specifications typical at +25c with v cc = +15v or +12v, v logic = +5v, v ee = -15v or -12v; parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits est ablished by characterization and are not production tested. parameter temperature range -5 (0c to +75c) units j suffix k suffix dynamic characteristics resolution (max) 12 12 bits linearity error +25c (max) 1 1 / 2 lsb 0c to +75c (max) 1 1 / 2 lsb max resolution for which no missing codes is guaranteed +25c 12 12 bits t min to t max 11 12 bits unipolar offset (max) adjustable to zero 2 1.5 lsb bipolar offset (max) v in = 0v (adjustable to zero) 4 4 lsb v in = -10v 0.15 0.1 % of fs full scale calibration error +25c (max), with fixed 50 resistor from ref out to ref in (adjustable to zero) 0.25 0.25 % of fs t min to t max (no adjustment at +25c) 0.475 0.375 % of fs t min to t max (with adjustment to zero +25c) 0.22 0.12 % of fs hi-574a, hi-674a
5 fn3096.6 august 7, 2008 temperature coefficients guaranteed max change, t min to t max (using internal reference) unipolar offset 2 1 lsb bipolar offset 2 1 lsb full scale calibration 9 2 lsb power supply rejection max change in full scale calibration +13.5v < v cc < +16.5v or +11.4v < v cc < +12.6v 2 1 lsb +4.5v < v logic < +5.5v 1 / 2 1 / 2 lsb -16.5v < v ee < -13.5v or -12.6v < v ee < -11.4v 2 1 lsb analog inputs input ranges bipolar -5 to +5 (note 6) v -10 to +10 (note 7) v unipolar 0 to +10 (note 6) v 0 to +20 (note 7) v input impedance 10v span 5k, 25% 20v span 10k, 25% power supplies operating voltage range v logic +4.5 to +5.5 v v cc +11.4 to +16.5 v v ee -11.4 to -16.5 v operating current i logic 7 typ, 15 max ma i cc +15v supply 11 typ, 15 max ma i ee -15v supply 21 typ, 28 max ma power dissipation 15v, +5v 515 typ, 720 max mw 12v, +5v 385 typ mw internal reference voltage t min to t max +10.00 0.05 max v output current, available for exter nal loads (external load should not change during conversion). 2.0 max ma dc and transfer accuracy specifications typical at +25c with v cc = +15v or +12v, v logic = +5v, v ee = -15v or -12v; parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits est ablished by characterization and are not production tested. (continued) parameter temperature range -5 (0c to +75c) units j suffix k suffix hi-574a, hi-674a
6 fn3096.6 august 7, 2008 8 dc and transfer accuracy specifications typical at +25c with v cc = +15v or +12v, v logic = +5v, v ee = -15v or -12v; parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits establ ished by characterization and are not production tested. (continued) parameter temperature range -2 (-55c to +125c) units s suffix t suffix dynamic characteristics resolution (max) 12 12 bits linearity error +25c 1 1 / 2 lsb -55c to +125c (max) 1 1 lsb max resolution for which no missing codes is guaranteed +25c 12 12 bits t min to t max 11 12 bits unipolar offset (max) adjustable to zero 2 1.5 lsb bipolar offset (max) v in = 0v (adjustable to zero) 4 4 lsb v in = -10v 0.15 0.1 % of fs full scale calibration error +25c (max), with fixed 50 resistor from ref out to ref in (adjustable to zero) 0.25 0.25 % of fs t min to t max (no adjustment at +25c) 0.75 0.50 % of fs t min to t max (with adjustment to zero at +25c) 0.50 0.25 % of fs temperature coefficients guaranteed max change, t min to t max (using internal reference) unipolar offset 2 1 lsb bipolar offset 2 2 lsb full scale calibration 20 10 lsb power supply rejection max change in full scale calibration +13.5v < v cc < +16.5v or +11.4v < v cc < +12.6v 2 1 lsb +4.5v < v logic < +5.5v 1 / 2 1 / 2 lsb -16.5v < v ee < -13.5v or -12.6v < v ee < -11.4v 2 1 lsb analog inputs input ranges bipolar -5 to +5 (note 6) v -10 to +10 (note 7) v unipolar 0 to +10 (note 6) v 0 to +20 (note 7) v input impedance 10v span 5k, 25% 20v span 10k, 25% power supplies operating voltage range v logic +4.5 to +5.5 v v cc +11.4 to +16.5 v v ee -11.4 to -16.5 v hi-574a, hi-674a
7 fn3096.6 august 7, 2008 operating current i logic 7 typ, 15 max ma i cc +15v supply 11 typ, 15 max ma i ee -15v supply 21 typ, 28 max ma power dissipation 15v, +5v 515 typ, 720 max mw 12v, +5v 385 typ mw internal reference voltage t min to t max +10.00 0.05 max v output current, available for exter nal loads (external load should not change during conversion). 2.0 max ma digital specifications all models, over full temperature range; parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits establ ished by characterization and are not production tested. parameter min typ max logic inputs (ce, cs , r/c , a o ,12/8 ) logic ?1? +2.4v - +5.5v logic ?0? -0.5v - +0.8v current - 0.1a 5a capacitance - 5pf - logic outputs (db11-db0, sts) logic ?0? (i sink - 1.6ma) - - +0.4v logic ?1? (i source - 500a) +2.4v - - logic ?1? (i source - 10a) +4.5v - - leakage (high-z state, db11-db0 only) - 0.1a 5a capacitance - 5pf - timing specifications (hi-574a) +25c, note 5, unless otherwise specified. symbol parameter min typ max units convert mode t dsc sts delay from ce - - 200 ns t hec ce pulse width 50 - - ns t ssc cs to ce setup 50 - - ns t hsc cs low during ce high 50 - - ns t src r/c to ce setup 50 - - ns t hrc r/c low during ce high 50 - - ns t sac a o to ce setup 0 - - ns t hac a o valid during ce high 50 - - ns t c conversion time 12-bit cycle t min to t max 15 20 25 s 8-bit cycle t min to t max 10 13 17 s dc and transfer accuracy specifications typical at +25c with v cc = +15v or +12v, v logic = +5v, v ee = -15v or -12v; parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits establ ished by characterization and are not production tested. (continued) parameter temperature range -2 (-55c to +125c) units s suffix t suffix hi-574a, hi-674a
8 fn3096.6 august 7, 2008 read mode t dd access time from ce - 75 150 ns t hd data valid after ce low 25 - - ns t hl output float delay - 100 150 ns t ssr cs to ce setup 50 - - ns t srr r/c to ce setup 0 - - ns t sar a o to ce setup 50 - - ns t hsr cs valid after ce low 0 - - ns t hrr r/c high after ce low 0 - - ns t har a o valid after ce low 50 - - ns t hs sts delay after data valid 300 - 1200 ns timing specifications (hi-674a) +25c, note 5, unless otherwise specified. symbol parameter min typ max units convert mode t dsc sts delay from ce - - 200 ns t hec ce pulse width 50 - - ns t ssc cs to ce setup 50 - - ns t hsc cs low during ce high 50 - - ns t src r/c to ce setup 50 - - ns t hrc r/c low during ce high 50 - - ns t sac a o to ce setup 0 - - ns t hac a o valid during ce high 50 - - ns t c conversion time 12-bit cycle t min to t max 81215s 8-bit cycle t min to t max 5810s read mode t dd access time from ce - 75 150 ns t hd data valid after ce low 25 - - ns t hl output float delay - 100 150 ns t ssr cs to ce setup 50 - - ns t srr r/c to ce setup 0 - - ns t sar a o to ce setup 50 - - ns t hsr cs valid after ce low 0 - - ns t hrr r/c high after ce low 0 - - ns t har a o valid after ce low 50 - - ns t hs sts delay after data valid 25 - 850 ns notes: 5. time is measured from 50% level of digi tal transitions. tested with a 50pf and 3k load. 6. for the ?10v input?, pin 13. 7. for the ?20v input?, pin 14. timing specifications (hi-574a) +25c, note 5, unless otherwise specified. (continued) symbol parameter min typ max units hi-574a, hi-674a
9 fn3096.6 august 7, 2008 definitions of specifications linearity error linearity error refers to the deviation of each individual code from a line drawn from ?zero? through ?full scale?. the point used as ?zero? occurs 1 / 2 lsb (1.22mv for 10v span) before the first code transition (all zeros to only the lsb ?on?). ?full scale? is defined as a level 1 1 / 2 lsb beyond the last code transition (to all ones). the dev iation of a code from the true straight line is measured from the middle of each particular code. the hi-x74ak grade is guaranteed for maximum nonlinearity of 1 / 2 lsb. for this grade, this means that an analog value which falls exactly in the center of a given code width will result in the correct digital output co de. values nearer the upper or lower transition of the code width may produce the next upper or lower digital output code. the hi-x74aj is guaranteed to 1 lsb max error. for this grade, an analog value which falls within a given code width will result in either the correct code for that region or either adjacent one. note that the linearity error is not user-adjustable. differential linearity error (no missing codes) a specification which guarant ees no missing codes requires that every code combination appear in a monotonic increasing sequence as the analog input level is increased. thus every code must have a finite width. for the hi-x74ak grade, which guarantees no missing codes to 12-bit resolution, all 4096 codes must be present over the entire operating temperature ranges. the hi-x74aj grade guaran tees no missing codes to 11-bit resolution over temperature; this means that all code combinations of the upper 11 bits must be present; in practice very few of the 12-bit codes are missing. unipolar offset the first transition should occur at a level 1 / 2 lsb above analog common. unipolar offset is defined as the deviation of the actual transition from that point. this offs et can be adjusted as discussed on the following pages. the unipolar offset temperature coefficient specif ies the maximum change of the transition point over temperat ure, with or without external adjustment. bipolar offset similarly, in the bipolar mode, the major carry transition (0111 1111 1111 to 1000 0000 0000) should occur for an analog value 1 / 2 lsb below analog common. the bipolar offset error and temperature coefficient specify the initial deviation and maximum change in the error over temperature. full scale calibration error the last transition (from 1111 1111 1110 to 1111 1111 1111) should occur for an analog value 1 1 / 2 lsb below the nominal full scale (9.9963v for 10.000v full scale). the full scale calibration error is the de viation of the actual level at the last transition from the ideal level. this error, which is typically 0.05 to 0.1% of full scale, can be trimmed out as shown in figures 1 and 2. the full scale calibration error over temperature is given wit h and without the initial error trimmed out. the temperature coefficients for each grade indicate the maximum change in the full scale gain from the initial value using the internal 10v reference. pin descriptions pin symbol description 1v logic logic supply pin (+5v) 2 12/8 data mode select - selects between 12-bit and 8-bit output modes. 3cs chip select - chip select high disables the device. 4a o byte address/short cycle - see table 3 for operation. 5r/c read/convert - see table 3 for operation. 6 ce chip enable - chip enable low disables the device. 7v cc positive supply (+12v/+15v) 8 ref out +10v reference 9 ac analog common 10 ref in reference input 11 v ee negative supply (-12v/-15v). 12 bip off bipolar offset 13 10v input 10v input - used for 0v to 10v and -5v to +5v input ranges. 14 20v input 20v input - used for 0v to 20v and -10v to +10v input ranges. 15 dc digital common 16 db0 data bit 0 (lsb) 17 db1 data bit 1 18 db2 data bit 2 19 db3 data bit 3 20 db4 data bit 4 21 db5 data bit 5 22 db6 data bit 6 23 db7 data bit 7 24 db8 data bit 8 25 db9 data bit 9 26 db10 data bit 10 27 db11 data bit 11 (msb) 28 sts status bit - status high implies a conversion is in progress. hi-574a, hi-674a
10 fn3096.6 august 7, 2008 temperature coefficients the temperature coefficients for full-scale calibration, unipolar offset, and bipolar offset specify the maximum change from the initial (25c) value to the value at t min or t max . power supply rejection the standard specifications fo r the hi-x74a assume use of +5.00v and 15.00v or 12.00v supplies. the only effect of power supply error on the performance of the device will be a small change in the full scale calibration. this will result in a linear change in all lower order codes. the specifications show the maximum change in calibration from the initial value with the supplies at the various limits. code width a fundamental quantity for a/d converter specifications is the code width. this is defined as the range of analog input values for which a given digital output code will occur. the nominal value of a code width is equivalent to 1 least significant bit (lsb) of the full scale range or 2.44mv out of 10v for a 12-bit adc. quantization uncertainty analog-to-digital converters ex hibit an inherent quantization uncertainty of 1 / 2 lsb. this uncertainty is a fundamental characteristic of the quantiz ation process and cannot be reduced for a converter of given resolution. left-justified data the data format used in the hi-x74a is left-justified. this means that the data represents the analog input as a fraction of full-scale, ranging from 0 to . this implies a binary point to the left of the msb. applying the hi-x74a for each application of th is converter, the ground connections, power supply bypassing, analog signal source, digital timing and signal routing on the circuit board must be optimized to assure maximum performance. these areas are reviewed in the following sections, along with basic operating modes and calibration requirements. physical mounting and layout considerations layout unwanted, parasitic circuit co mponents, (l, r, and c) can make 12-bit accuracy impossible, even with a perfect a/d converter. the best policy is to eliminate or minimize these parasitics through proper circuit layout, rather than try to quantify their effects. the recommended construction is a double-sided printed circuit board with a ground plane on the component side. other techniques, such as wire -wrapping or point-to-point wiring on vector board, will hav e an unpredictable effect on accuracy. in general, sensitive analog signals should be routed between ground traces and kept well away from digital lines. if analog and digital lines must cross, they should do so at right angles. power supplies supply voltages to the hi-x74a (+15v, -15v and +5v) must be ?quiet? and well regulated. voltage spikes on these lines can affect the converter?s accuracy, causing several lsbs to flicker when a constant input is applied. digital noise and spikes from a switching power supply ar e especially troublesome. if switching supplies must be used, outputs should be carefully filtered to assure ?quiet? dc vo ltage at the converter terminals. further, a bypass capacitor pair on each supply voltage terminal is necessary to counter the effect of variations in supply current. connect one pair from pin 1 to 15 (v logic supply), one from pin 7 to 9 (v cc to analog common) and one from pin 11 to 9 (v ee to analog common). for each capacitor pair, a 10f tantalum type in parallel with a 0.1f ceramic type is recommended. ground connections pins 9 and 15 should be tied together at the package to guarantee specified per formance for the converter. in addition, a wide pc trace should run directly from pin 9 to (usually) +15v common, and from pin 15 to (usually) the +5v logic common. if the converter is located some distance from the system?s ?single point? ground, make only these connections to pins 9 and 15: tie them together at the package, and back to the system ground with a single path. this path should have low resistance. (code dependent currents flow in the v cc , v ee and v logic terminals, but not through the hi-x74a?s analog common or digital common). analog signal source hi-574a and hi-674a the device chosen to drive the hi-x74a analog input will see a nominal load of 5k (10v range) or 10k (20v range). however, the other end of these input resistors may change 400mv with each bit decision, creating abrupt changes in current at the analog input. thus, the signal source must maintain its output voltage while furnishing these step changes in load current, which occur at 1.6 s and 950ns intervals for the hi-574a and hi-674a, respectively. this requires low output impedance and fast settling by the signal source. the output impedance of an op amp, for example, has an open loop value which, in a closed loop, is divided by the loop gain available at a frequency of interest. the amplifier should have acceptable loop gain at 600khz for use with the hi-x74a. to check whether the output properties of a signal source are suitable, monitor the hi-x74a?s input (pin 13 or 14) with an oscilloscope while a conversion is in progress. each of the twelve disturbances should subside in 1 s or less for the hi-574a and 500ns or less for the hi-674a. (the comparator decision is made about 1.5s and 850ns after each code change from the sar for the hi-574a and hi-674a, respectively.) 4095 4096 hi-574a, hi-674a
11 fn3096.6 august 7, 2008 if the application calls for a sample/hold to precede the converter, it should be noted that not all sample/holds are compatible with the hi-574a in the manner described above. these will require an additional wideband buffer amplifier to lower their output impedance. a simpler solution is to use the intersil ha-5320 sample/hold, which was designed for use with the hi-574a. range connections and calibration procedures the hi-x74a is a ?complete? a/d converter, meaning it is fully operational with addition of the power supply voltages, a start convert signal, and a few external components as shown in figures 1 and 2. nothing more is required for most applications. whether controlled by a proc essor or operating in the stand-alone mode, the hi-x74a offers four standard input ranges: 0v to +10v, 0v to +20v, 5v and 10v. the maximum errors for gain and offset are listed under specifications. if required, however, these errors may be adjusted to zero as explained below. power supply and ground connections have been discussed in an earlier section. unipolar connections and calibration refer to figure 1. the resistors shown (see note below) are for calibration of offset and gain. if this is not required, replace r2 with a 50 , 1% metal film resistor and remove the network on pin 12. connect pin 12 to pin 9. then, connect the analog signal to pin 13 for the 0v to 10v range, or to pin 14 for the 0v to 20v range. inputs to +20v (5v over the power supply) are no problem - the converter operates normally. calibration consists of adjusting the converter?s most negative output to its ideal valu e (offset adjustment), then, adjusting the most positive output to its ideal value (gain adjustment). to understand t he procedure, note that in principle, one is setting the output with respect to the midpoint of an increment of analog input, as denoted by two adjacent code changes. nominal value of an increment is one lsb. however, this approach is impractical because nothing ?happens? at a midpoint to indicate that an adjustment is complete. therefore, calibration is performed in terms of the observable code changes instead of the midpoint between code changes. for example, midpoint of t he first lsb increment should be positioned at the origin, with an output code of all 0?s. to do this, apply an input of + 1 / 2 lsb (+1.22mv for the 10v range; +2.44mv for the 20v range). adjust the offset potentiometer r1 until the first code tr ansition flickers between 0000 0000 0000 and 0000 0000 0001. next, perform a gain adjust at positive full scale. again, the ideal input corresponding to the last code change is applied. this is 1 1 / 2 lsbs below the nominal full scale (+9.9963v for 10v range; +19.9927v for 20v range). adjust the gain potentiometer r2 for flicker between codes 1111 1111 1110 and 1111 1111 1111. bipolar connections and calibration refer to figure 2. the gain a nd offset errors listed under specifications may be adjusted to zero using potentiometers r1 and r2 (see note below). if this isn?t ? when driving the 20v (pin 14) input, minimize capacitance on pin 13. figure 1. unipolar connections ? when driving the 20v (pin 14) input, minimize capacitance on pin 13. figure 2. bipolar connections 10 ref in 8ref out 12 bip off 13 10v in 14 20v in ? 9 ana 16-19 low bits 20-23 middle bits 24-27 high bits sts 28 212/8 3cs 4a o 5r/c 6ce +5v 1 +15v 7 -15v 11 dig com 15 -15v offset r1 100k +15v gain r2 100 100k 100 0v to +10v analog inputs 0v to +20v com 16-19 low bits 20-23 middle bits 24-27 high bits sts 28 +5v 1 +15v 7 -15v 11 dig com 15 gain r2 100 100 5v analog inputs 10v offset 10 ref in 8ref out 12 bip off 13 10v in 14 20v in ? 9 ana 2 12/8 3cs 4a o 5r/c 6ce com r1 hi-574a, hi-674a
12 fn3096.6 august 7, 2008 required, either or both pots may be replaced by a 50 , 1% metal film resistor. connect the analog signal to pin 13 for a 5v range, or to pin 14 for a 10v range. calibration of offset and gain is similar to that for the unipolar ranges as discussed above. first apply a dc input voltage 1 / 2 lsb above negative full scale (i.e., -4.9988v for the 5v range, or -9.9976v for the 10v range). adjust the offset potentiometer r1 for flicker between output codes 0000 0000 0000 and 0000 0000 0001. next, apply a dc input voltage 1 1 / 2 lsbs below positive full scale (+4.9963v for 5v range; +9.9927v for 10v range). adjust the gain potentiometer r2 for flicker between codes 1111 1111 1110 and 1111 1111 1111. note: the 100 potentiometer r2 provides gain adjust for the 10v and 20v ranges. in some applications, a full scale of 10.24v (lsb equals 2.5mv) or 20.48v (lsb equals 5.0mv) is more convenient. for these, replace r2 by a 50 , 1% metal film resistor. then, to pro- vide gain adjust for the 10.24v range, add a 200 potentiometer in series with pin 13. for the 20.48v range, add a 500 potentiometer in series with pin 14. controlling the hi-x74a the hi-x74a includes logic for direct interface to most microprocessor systems. the processor may take full control of each conversion, or the converter ma y operate in the ?stand-alone? mode, controlled only by the r/c input. full control consists of selecting an 8-bit or 12-bit conversion cycle, initiating the conversion, and reading the output data when ready-choosing either 12 bits at once or 8 followed by 4, in a left-justified format. the five control inputs are all ttl/cmos-compatible: (12/8 , cs , a o , r/c and ce). table 3 illustrates the use of these inputs in controlling the converter?s operations. also, a simplified schematic of the internal control logic is shown in figure 6. ?stand-alone operation? the simplest control interface calls for a single control line connected to r/c . also, ce and 12/8 are wired high, cs and a o are wired low, and the output data appears in words of 12 bits each. the r/c signal may have any duty cycle within (and including) the extremes shown in figures 7 and 8. in general, data may be read when r/c is high unless sts is also high, indicating a conversion is in progress. timing parameters particular to this mode of operation are listed in tables 1 and 2. conversion length a convert start transition (see table 1) latches the state of a o , which determines whether the conversion continues for 12 bits (a o low) or stops with 8 bits (a o high). if all 12 bits are read following an 8-bit conversion, the last three lsbs will read zero and db3 will read one. a o is latched because it is also involved in enabling the output buffers (see ??reading the output data? on page 13). no other control inputs are latched. table 1. hi-574a stand-alone mode timing symbol parameter min typ max units t hrl low r/c pulse width 50 - - ns t ds sts delay from r/c - - 200 ns t hdr data valid after r/c low 25 - - ns t hs sts delay after data valid 300 - 1200 ns t hrh high r/c pulse width 150 - - ns t ddr data access time - - 150 ns time is measured from 50% level of digital transitions. tested with a 50pf and 3k load. table 2. hi-674a stand-alone mode timing symbol parameter min typ max units t hrl low r/c pulse width 50 - - ns t ds sts delay from r/c - - 200 ns t hdr data valid after r/c low 25 - - ns t hs sts delay after data valid 25 - 850 ns t hrh high r/c pulse width 150 - - ns t ddr data access time - - 150 ns time is measured from 50% level of digital transitions. tested with a 50pf and 3k load. table 3. truth table for hi-x74a control inputs ce cs r/c 12/8 a o operation 0 x x x x none x 1 x x x none 0 0 x 0 initiate 12-bit conversion 0 0 x 1 initiate 8-bit conversion 1 0 x 0 initiate 12-bit conversion 1 0 x 1 initiate 8-bit conversion 10 x 0 initiate 12-bit conversion 10 x 1 initiate 8-bit conversion 1 0 1 1 x enable 12-bit output 1 0 1 0 0 enable 8 msbs only 1 0 1 0 1 enable 4 lsbs plus 4 trailing zeroes hi-574a, hi-674a
13 fn3096.6 august 7, 2008 conversion start a conversion may be initiated as shown in table 3 by a logic transition on any of three inputs: ce, cs or r/c . the last of the three to reach the correct state starts the conversion, so one, two or all three may be dynamically controlled. the nominal delay from each is the same, and if necessary, all three may change state simultaneously. however, to ensure that a particular input controls the start of conversion, the other two should be set up at least 50ns earlier. see the hi-x74a timing specifications, convert mode. this variety of hi-x74a cont rol modes allows a simple interface in most system appl ications. the convert start timing relationships are illustrated in figure 3. the output signal sts indicates status of the converter by going high only while a conversion is in progress. while sts is high, the output buffers remain in a high impedance state and data cannot be read. also, an additional start convert will not reset the converter or re-initiate a conversion while sts is high. reading the output data the output data buffers remain in a high impedance state until four conditions are met: r/c high, sts low, ce high and cs low. at that time, data lines become active according to the state of inputs 12/8 and a o . timing constraints are illustrated in figure 4. the 12/8 input will be tied high or low in most applications, though it is fully ttl/cm os-compatible. with 12/8 high, all 12 output lines become active simultaneously, for interface to a 12-bit or 16-bit data bus. the a o input is ignored. with 12/8 low, the output is organized in two 8-bit bytes, selected one at a time by a o . this allows an 8-bit data bus to be connected as shown in figure 5. a o is usually tied to the least significant bit of the address bus, for storing the hi-x74a output in two consecutive memory locations. (with a o low, the 8 msbs only are enabled. with a o high, 4 msbs are disabled, bits 4 through 7 are forced low, and the 4 lsbs are enabled). this two byte format is considered ?left justified data,? for which a decimal (or binary!) point is assumed to the left of byte 1: further, a o may be toggled at any time without damage to the converter. break-before-make action is guaranteed between the two data bytes, which assures that the outputs strapped together in figure 5 will never be enabled at the same time. a read operation usually begins after the conversion is complete and sts is low. for earliest access to the data, however, the read should begin no later than (t dd + t hs ) before sts goes low. see figure 4. byte 1 byte 2 ? xxxxxxxx xxxx0 0 0 0 msb lsb see hi-x74a timing specifications for more information. figure 3. convert start timing see hi-x74a timing specifications for more information. figure 4. read cycle timing ce cs r/c a o sts db11-db0 t ssc t src t hec t hsc t sac t hac t dsc t c high impedance t hrc ce cs r/c a o sts db11-db0 high impedance t ssr t srr t sar t hs t hd t hl t dd t har t hrr t hsr data valid hi-574a, hi-674a
14 fn3096.6 august 7, 2008 figure 5. interface to an 8-bit data bus 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 sts db11 (msb) db0 (lsb) dig. com. hi-x74a 12/8 a o a o data bus address bus figure 6. hi-x74a control logic d ck q q eoc13 eoc9 ce r/c a o cs 12/8 input buffers read control power up reset convert control current controlled oscillator nibble b zero override nibble a, b nibble c status strobe clock reset a o latch hi-574a, hi-674a
15 fn3096.6 august 7, 2008 figure 7. low pulse for r/c - outputs enabled after conversion figure 8. high pulse for r/c - outputs enabled while r/c high, otherwise high-z t hrl t ds t hdr t c t hs r/ c sts db11-db0 valid data valid data t c t hdr t ddr t hrh t ds valid data r/ c sts db11-db0 high-z high-z hi-574a, hi-674a
16 fn3096.6 august 7, 2008 die characteristics die dimensions: analog: 3070mm x 4610mm digital: 1900mm x 4510mm metallization: digital type: nitrox thickness: 10k ? 2k ? metal 1: alsicu thickness: 8k ? 1k ? metal 2: alsicu thickness: 16k ? 2k ? analog type: al thickness: 16k ? 2k ? passivation: type: nitride over silox nitride thickness: 3.5k ? 0.5k ? silox thickness: 12k ? 1.5k ? worst case current density: 1.3 x 10 5 a/cm 2 metallization mask layout hi-574a, hi-674a analog common db10 analog common analog common v refin v ee v refout v cc ce r/ c a o cs bipolar offset 10v in 20v in db9 db8 db7 db6 db5 db4 db3 db2 db0 db1 12/ 8 v logic sts db11 v logic digital common hi-574a, hi-674a
17 fn3096.6 august 7, 2008 hi-574a, hi-674a ceramic dual-in-line me tal seal packages (sbdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead dimensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this c onfiguration dimension b3 replaces dimension b2. 5. dimension q shall be measured from the seating plane to the base plane. 6. measure dimension s1 at all four corners. 7. measure dimension s2 from the top of the ceramic body to the nearest metallization or lead. 8. n is the maximum number of terminal positions. 9. braze fillets shall be concave. 10. dimensioning and tolerancing per ansi y14.5m - 1982. 11. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane s s -d- -a- -c- e a -b- aaa ca - b m d s s ccc ca - b m d s s d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 s2 m a d28.6 mil-std-1835 cdip2-t28 (d-10, configuration c) 28 lead ceramic dual-in-line metal seal package symbol inches millimeters notes min max min max a - 0.232 - 5.92 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 1.490 - 37.85 - e 0.500 0.610 12.70 15.49 - e 0.100 bsc 2.54 bsc - ea 0.600 bsc 15.24 bsc - ea/2 0.300 bsc 7.62 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 5 s1 0.005 - 0.13 - 6 s2 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2 n28 288 rev. 0 5/18/94
18 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn3096.6 august 7, 2008 hi-574a, hi-674a dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the in ch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are m easured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e28.6 (jedec ms-011-ab issue b) 28 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.250 - 6.35 4 a1 0.015 - 0.39 - 4 a2 0.125 0.195 3.18 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.030 0.070 0.77 1.77 8 c 0.008 0.015 0.204 0.381 - d 1.380 1.565 35.1 39.7 5 d1 0.005 - 0.13 - 5 e 0.600 0.625 15.24 15.87 6 e1 0.485 0.580 12.32 14.73 5 e 0.100 bsc 2.54 bsc - e a 0.600 bsc 15.24 bsc 6 e b - 0.700 - 17.78 7 l 0.115 0.200 2.93 5.08 4 n28 289 rev. 1 12/00

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